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|Modeling and Reliability Analysis of TSVs for High Frequency Applications|
|Keywords: TSV, Thermomechanical Delamination, S-parameter Simulation|
|Through Silicon Via (TSV) technology offers a wide range of advantages over conventional interconnect schemes. TSV technology is used in 3D ICs for high frequency (77 GHz) RADAR applications. However, TSVs are associated with reliability issues due to thermo-mechanical delamination which has long been a fundamental bottleneck in implementing TSVs as 3D interconnects . Thermo-mechanical delamination act as parasitics which adversely affect the electrical characteristics of the TSV. Therefore, only mechanical modeling of TSV to mitigate this reliability issue is insufficient. It is very crucial to perform electrical modeling of thermo-mechanical delaminations. Thermal annealing cycles in copper TSVs indicate that, for sufficient annealing temperatures, plastic yield within the copper leads to substantial residual stress in the neighboring silicon following cool-down . This residual stress can result in the formation and growth of 1) radial crack in silicon during heating when circumferential stress is tensile; 2) circumferential crack in silicon during cooling when radial stress is tensile; 3) interfacial crack during both heating and cooling resulting in TSV pop-up . This paper presents electrical modeling of thermo-mechanical delamination in TSV. Previously, several papers in electrical modeling of TSV have been published in open literature; however, these do not consider the thermal-mechanical delamination in TSV. Stress-induced thermo-mechanical delamination in TSV has been analyzed by considering the thermo-mechanical stress loading effects of high aspect ratio copper electroplated TSVs. Two-dimensional mechanical finite element models have been built to analyze the stress distribution in TSV structures. These mechanical models are used to perform Abaqus simulations to compute the energy release rate at the crack when stress is applied, and to track the propagation of crack over different thermal cycles. The mechanical models and energy release rate at the crack are then translated to electrical defect models to evaluate the functional electrical performance of TSVs with delaminations. To test these electrical defect models for high frequency applications a continuous wave input signal was applied to the TSV and the delamination acting as a parasitic resulted in attenuation of RF power at the output of the TSV. Two different case studies were considered during for simulations; interfacial delaminations between TSV metal and insulating layer, and radial or circumferential cracks in silicon surrounding the TSV. Simulation was performed using an RF signal with -15 dBm power on a crack length of 0.2 um and width of 0.15 um. We observed output power of -11.2 dBm at a frequency of 150 GHz. When the crack length was increased, the output power decreased to -8.32 dBm due to increased parasitics resulting in more attenuation of RF output. This reliability analysis enables us to evaluate the electrical performance of TSVs.|
|Kaushal Kannan, Graduate Research Assistant
City College of New York
New York, NY