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Redistribution Layers (RDLs) for 3D IC Integration
Keywords: 3D IC integration, re-distribution layer, TSV
One of the potential applications of 3D IC integration is wide I/O interface, which consists of a piece of device-less silicon with through-silicon vias (TSVs) and high-performance and high-density integrated circuit (IC) chips without TSV. This piece of TSV silicon (also called passive interposer) can be used to support chips on its top-side as well as its bottom-side. The lateral communication of the chips on either the top-side or the bottom-side is through the redistribution layers (RDLs) of the interposer, which is an integral part of 3D IC integration. There are at least two methods to fabricate the RDLs. One is by using polymers (such as polyimide or benzocyclobutene) to make the passivation layer and electroplating (such as Cu) to make the metal layer. The other is by using the Cu damascene technique which is primarily modified from the conventional BEOL (back-end-of-line) to make the Cu metal layers. In this study, the materials and processes of fabricating RDLs (as much as 3 RDLs on its top-side and 2 RDLs on its bottom-side) of passive interposers by both methods are presented. The advantages and disadvantages of each method are examined and their limitations, issues and possible solutions are provided.
John H. Lau,
ITRI
Chutung, Hsinchu, Taiwan
USA


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