Micross

Abstract Preview

Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Size Matters - Embedding as an Enabler of Next-Generation SiPs
Keywords: Embedding, SiP, Reliability
Embedding is a relatively new packaging technology involving the use of (for example) laminates to encapsulate the active and/or passive component, as well as PCB and/or SMT processes for electrical connections. The embedded system can be used in that condition, or further processed to create a System-in-Package (or System-in-Board in case of larger assemblies). In that last case, the SiP (respectively SiB) is treated like any other substrate (respectively PCB). In the search for higher integration, embedding is gaining traction as an alternative 3D-packaging solution, due to its multiple advantages: high integration, large production format, intrinsic matching to PCB in terms of pitch and CTE characteristics, mechanical stability and possibility to adapt substrate properties based on specific requirements (Dk, thermal conductivity…). The various players in the field are raking in new design-ins, and production volumes are rapidly increasing. Those characteristics mean that embedded packages are directly competing with several other packaging architectures routinely used in smartphone applications: - Almost as small as WL-CSPs while being more robust and offering better thermal behavior, - Smaller than QFNs with similar thermal properties, - Thinner than PoPs while allowing easier 3D integration, - SiP architecture to decrease PCB-level cost-of-ownership. Smartphone manufacturers are constantly demanding increased reliability and performance, while requesting from packages to enable higher functionalities in smaller form factors. Several test vehicles were developed incorporating one or more embedded Si dice and passives in the substrate, and the same number of WL-CSP and SMT passives on top to mimic the PoP architecture it intends to replace. This document presents the latest advancements (architectures and functionalities) in ECP® technology, as well as the qualification results for various package and die sizes to JESD22. The test vehicle additionally allows comparing reliability results between surface-mounted devices and embedded ones. Ease of integration down the supply chain is confirmed by Moiré interferometry.
Nick Renaud-Bezot, Product Manager
AT&S
Leoben, Styria
Austria


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems