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Droplet-on-demand inkjet-filled TSVs as a pathway to cost-efficient chip stacking
Keywords: Drop-on-demand Inkjet, TSV, Metal Nanoparticle
Through-silicon vias (TSVs) are widely recognized as one of the critical enabling components for three-dimensional integration and chip-stacking. TSVs have already seen limited deployment in advanced chip-stacked packages, though the technology is still evolving. To date, copper electroplating [3], tungsten CVD [2], and highly-doped and isolated silicon columns [4] have all been used to fabricate high-aspect ratio vertical interconnects that extend through entire wafers. These approaches are all tuned for wafer-scale processing flows, require multiple processing steps, and require large volumes of materials to fabricate the final features. As a result, while TSVs have achieved some initial successes, significant cost scaling is required to make the technology more pervasive. A via filling strategy that 1) scales well for medium- to high-density TSV layouts, 2) requires minimal materials, 3) maintains thermal budget restrictions established for back-end-of-line (BEOL) processing, and 4) enables both die-scale and wafer-scale fabrication compatibility will be a particularly impactful achievement. As a solution to the problems described, we present inkjet printing with metallic nanoparticle inks as a novel technique used both to fill and bump TSVs in a single process step. Nanoparticle inks are attractive for TSV filling since they deliver high conductivities at low sintering temperatures, and also show excellent mechanical and thermal reliability [1]. We have previously reported on their use in bump / post formation for conventional flip chip applications. Here, for the first time, we demonstrate TSV filling and bumping using these same materials [5]. Using 100 µm deep DRIE trenches, we have successfully filled and bumped TSVs in one process step. We have then successfully achieved die bonding using thermo-compression bonding to realize strong, mechanically-robust TSV structures. Cross-sectional SEM analysis shows void-free filling for individual TSVs as well as void-free bonding between two TSVs. We have bonded arrays of the filled and bumped TSVs and will present mechanical and electrical performance results for both individual TSVs as well as fully-bonded die as a function of sintering conditions. Due to the very specific geometry associated with TSV trenches, we will discuss the impacts this confined space will have on the ability for nanoparticle systems to fully sinter, reflow, and form robust bonds between stacked layers in order to confirm the long-term utility of inkjet-based processes in TSV chip-stacking process flows.
Jacob Sadie,
University of California, Berkeley
San Francisco, CA

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