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Application of Low-k Liner for Stress and Capacitance Control in Cu-TSV
Keywords: TSV, low-k liner, capacitance
Through silicon via (TSV) has emerged as an essential enabler for the next generation of integrated circuits and systems for continuous performance growth (“More Moore”) and functional diversification (“More than Moore”). TSV is commonly fabricated by high aspect ratio deep silicon etching, lining with dielectric layer for electrical isolation and super-conformal filing with copper hence forming a MOS structure. It has been reported that Cu-TSV can exert thermo-mechanical stress on Si due to CTE mismatch. This stress can result in undesired device mobility variation and interconnect distortion. In addition, TSV parasitic capacitance has the most predominant impact on the circuit operation. It is therefore imperative to reduce the TSV stress and capacitance. One solution is to use low-k dielectric as the liner since it has much lower elastic modulus and effective permittivity. In this work, low-k dielectric is successfully integrated in TSV as a liner. The implications on TSV stress, capacitance and leakage current are discussed. The current results demonstrate that the miniaturization of the TSV dimension is not the only way to reduce the thermo-mechanical stress in Si surrounding the TSV structure due to the lower Cu volume. It is also possible to control the stress level via the selection of a suitable liner material with a lower elastic modulus. The interesting findings in this work can be attributed to the fact that the choice of a lower Young’s modulus and a porous dielectric liner material could effectively reduce the near-surface compressive stress in Si by >25% compared with the conventional liner such as PETEOS which is more rigid. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved with low-k material which has an effective dielectric constant of ~2.8 integrated in the TSV as liner. Low-k liner with conformal step coverage is successfully achieved in our fabrication process. Upon testing, it is found that the integration of the low-k liner reduces the TSV capacitance by ~28% as compared with the conventional PETEOS oxide liner. Furthermore, IV measurements are carried out to monitor and study the leakage of the low-k liner. No abrupt breakdown is observed until at least at an electric field of 3MV/cm which corresponds to 60 V. In addition, annealing of the TSV in forming gas (N2/H2) at 350oC for 30 min successfully reduces the leakage current density by ~1.6X, to a mid-distribution value of ~6.8 x 10-6 A/cm2. In summary, this work has provided evidence of the technical merits of a low-k material to mitigate the undesired Cu-TSV induced stress in the surrounding Si and the related parasitic capacitance.
Chuan Seng Tan,
Nanyang Technological University
Singapore, Singapore

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