Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|IMPROVEMENT OF BACKSIDE SURFACE DEFECTS AND WAFER STRENGTH|
|Keywords: Wet etch process, Backside defect removal, Wafer strength|
|The ever accelerating race to keep up with Moore’s law with aggressive device scaling, shrinking ground rules and need for novel materials dictates ever tighter semiconductor process fidelity. That is - on the front side of the wafer. Measurably less attention is being paid to the wafer back side. Backside wafer defects have been shown to reduce yield by leading to die breakage during packaging processes. Scratches and voids formed on the backside of the wafer during various manufacturing processes create weak spots on the wafer, which later act as centers of die crack generation and propagation. In this paper, we will report the technical details of a wet etch backside clean process. The process is set up on a single wafer wet etch tool within the confines of IBM’s 300 mm fab. It works by removing the outer layer of the backside of the Si wafer which has become defective and damaged by prior tool processing. This new defect removal process increases die strength (wafer mechanical strength) and removes surface defects from the backside of the wafer. Our studies show that by removing 15-30 microns from the wafer backside leads to removal of 90% of cosmetic defects on the back side of the wafer and a 60% increase in die strength when using this process. We characterized the process and its effects on the wafer cosmetic and mechanical properties (data on physical and chemical characterization such as atomic force microscopy, X-ray photoelectron spectroscopy, bright-field defect inspection, warpage, thickness, thermal interface material adhesion test, and die strength is included). We also built and stressed modules from several technology nodes and showed them behaving on par or slightly better than process of record hardware. Based on our data – developed process is a viable method of controlling wafer backside defectivity and die strength.|
|Victoria L. Calero-DiazdelCastillo, FBEOL integration Engineer
Hopewell Junction, NY