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Improving WLCSP Reliability Through Optimization of Design and Construction Factors
Keywords: WLCSP, reliability, bumps
Wafer-level chip scale packaging (WLCSP) offers the smallest package form factor and has become a preferred option for the handheld consumer electronics space where portability and increasing functionality are strong drivers. WLCSPs also continue to migrate into other applications requiring small size, high performance, and low cost. In WLCSP technology, chip I/Os are generally fanned-in across the die surface using thick polymer and redistribution line (RDL) buildup layers to produce an area array, and large solder bumps are then formed at the terminals by ball drop or plating. These additive processes allow the chip to be attached directly to a printed circuit board (PCB) with good reliability. The thermal mismatch between the silicon chip and the organic PCB has limited WLCSPs to relatively small die sizes — usually less than 5×5mm2 — so WLCSP suppliers and users are continually looking for ways to improve reliability and extend the size range of chips that can utilize this unique packaging technology. In recent years, the introduction of new polymers and solder alloys have extended the usable die sizes into the 5×5mm2 to 6×6mm2 range. Further significant increases are likely to require new and novel WLCSP structures and approaches. Optimizing the solder joint geometry and the WLCSP buildup layer thicknesses are relatively simple but effective ways to improve WLCSP reliability. Important geometric variables to consider include the size of the RDL capture pad and via under the bump on the WLCSP, the size of the WLCSP under bump metallurgy (UBM) pad, and the size of the corresponding pad on the PCB. Thicknesses of the RDL and polymer buildup layers on the WLCSP also can play a significant role. Optimizing these factors can lead to performance improvements in thermal cycling and drop, the two key board-level reliability tests that predict the life of the WLCSP. The effects of solder joint geometry and buildup layer thicknesses on WLCSP reliability have been studied here both through simulations and board level reliability (BLR) testing. In the actual BLR tests, an enhancement of nearly 2× was achieved in thermal cycling reliability by optimizing the solder joint and UBM pad stack geometries. In particular, undersizing the PCB pad to produce a more spherical joint geometry appears to be very important for optimizing thermal cycling results. The effects of thicker polymer and RDL buildup layers were studied and these results also will be presented. Changes such as these can generally be implemented and performance improvements achieved without the need for introducing new materials sets and processes, an often costly proposition.
Boyd Rogers, VP of R&D
Deca Technologies
Tempe, AZ

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