Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Lithography Process Optimization for 3D and 2.5D Applications|
|Keywords: Through-Silicon Via , Redistribution Layer, Lithography|
|Lithography process optimization is a key technology enabling mass production of high-density interconnects using 3D and 2.5D technologies. In this paper, Canon will continue its discussion of lithography optimization of thick-resist profiles and overlay accuracy to increase process margins for Through-Silicon Via (TSV) and Redistribution Layer (RDL) applications. Canon will also provide updates on the FPA-5510iV and FPA-5510iZ i-line steppers that are gaining acceptance as high-resolution, and low-cost lithography solutions for aggressive advanced packaging, 3D and 2.5D applications.|
|Doug Shelton, Sales & Marketing Manager
Canon U.S.A., Inc.
San Jose, CA