Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Assembly and Packaging enabling System Integration|
|Keywords: eWLB, System-in-Package, More than Moore|
|Only few companies are able to follow the ever more expensive path of Moore’s law. Today, we do not only reach cost constraints but also constraints in power and performance. New materials and innovative device developments are required. Assembly and Packaging with new developments helps to keep the path. In Europe, in contrast, the trend towards More than Moore is of increasing importance. More than Moore includes analog devices, RF, sensor & MEMS components, power chips, bio-chip, i.e. those technologies where Europe has a strong position. System-in-Package (SiP) is a rapidly evolving technology entering more and more into mass production. Examples are not only processors and memory, but also SiP for sensors/MEMS, power electronics, industrial products etc. We observe an ever more merging of silicon wafer technologies with assembly and packaging technologies, and even with board technologies. Today a coherent development taking into account chip, package, and board is needed. In this paper we provide examples of outstanding developments that emerged in packaging driven especially from Europe to tackle requirements from various markets. We start with developments of the so-called thin small leadless package (TSLP) of Infineon, a leadless package that can be made thinner than VQFN with smaller contacts of less parasitic effects. Molding and leadframe design played a key role for this package development. A fine filler mold compound was applied to fill the narrow spaces between package and demonstrated the excellent performance for electronic components. Next we introduce developments in wafer level packaging (WLP) technologies. Limitations in pin count of standard WLP packages lead to the development of the embedded wafer level ball grid array (eWLB). The eWLB approach is an approach which introduced new technologies like wafer level molding, but also technologies from the Si wafer technology like lithography for thin film processing. Another technology pushed a lot in Europe for various applications is the through silicon via (TSV) technology, which allows short contacts and highest miniaturization. In addition chip embedding in board type technologies is a major trend. All these technologies support integration towards ever more compact SiP solutions. The eWLB technology was developed during recent years to allow higher and higher system integration: Bricks developed were vertical through encapsulant via (TEV) contacts e.g. by electroplating, double sided eWLB with two dielectric layers on both sides, integration of discrete passives, passives designed by special interconnect architectures, or integration of antennas into the package. Continuous process innovation, introduction of new materials, and understanding of interfaces are required. More and more complexity to manage them is an outstanding challenge today. Those companies that are able to manage the complexity will be best in class.|