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Organic Chip Scale Package (CSP) Development for Flip Chip Applications
Keywords: Flip Chip, Chip Scale Package, CTE
This paper describes Chip Scale Packaging (CSP) development and evaluates the organic laminate material. Chip scale packaging can combine the strengths of various packaging technologies, such as the size and performance advantage of bare die assembly and the reliability of encapsulated devices. Optimizing the organic material for low CTE reduces the dimensional mis-match between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI). A typical CSP process starts with the mounting of the die on the laminate. For flip chip bumps, this is leadfree Sn-Ag attach. The flip chip assembly is then underfilled. Solder ball interconnects are added to provide second level assembly connection. Modeling laminate CSP groundrules with the organic material parameters provides stress and strain prediction as well highlighting BA process capability. Material properties must meet competing environmental, mechanical, thermal, and reliability needs for optimum performance of the package. Utilizing a low CTE material significantly reduces the strain in the solder joints during the reflow process. Predicted global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated. Electrical and mechanical tests carried out on the low CTE laminate material and subsequently on the related CSP are described. Recommendations for future CSP development and testing are presented.
Tomoyuki Yamada, Senior Field Applications Engineer
Kyocera SLC Technologies
Fishkill, NY
USA


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