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|High Bandwidth PoP|
|Keywords: PoP, Package-on-Package, High Bandwidth|
|Package-on-package (PoP) is widely used in smartphone to integrate application processor and memory. Due to the widespread of smartphones, the content of communication is rapidly changing from text to picture and video, which creates an insatiable demand for bandwidth. For example, today’s two-channel LPDDR3 with 1.6Gbps data rate provides 12.8GBs bandwidth, which allows streaming 1080p (120fps, 2.4Mpix, 3D) HD video on displays. With the push for higher image quality such as 240fps and 5Mpix video, the demand for bandwidth is needed to be doubled. In order to get bandwidth increased, one way is to increase memory data rate, the other is to increase the number of data I/O. Through silicon vias (TSVs) has been long considered as a possible solution to provide such bandwidth. It not only allows scaling of process-memory interconnects to 1200 at wide I/O level but also provides a significant reduction of power. However, the implementation of TSV is somehow constrained by thermal management, manufacturability, cost, and business model. Therefore, an improvement of current PoP structure to increase the number of interconnects becomes very important and imperative. In this work, three PoP structures are proposed to achieve the goal of increasing processor-memory interconnects. All of them are equipped with a pre-fabricated substrate interposer to allow the freedom of memory selections. The three PoP structures include two important features. First, it allows scaling of interconnects. The number of interconnect can be gradually increased from current 200+ to 1200 on a popular 14x14 PoP with different interconnect pitches. Secondly, this innovation can be achieved using currently available assembly manufacturing systems without adding extra cost like TSV technology does. There are three options for interconnect materials depending on the pitches. The interconnect can be made by either pure solder or Cu to solder or Cu to Cu bumps. The proposed options are able to provide the scalability of interconnect pitches from 0.27, 0.20 and even down to 0.13mm. The latter one allows 1200 interconnects on a 14x14mm PoP. The intention of this study is to investigate warpage, thermal and electrical performance of the proposed structures. Construction study and reliability assessment of each structure will be made. Finally and most importantly, manufacturability of each structure using currently available assembly equipment will be assessed and discussed.|
|Jason Cho, VP Eng
ASE (US), Inc.