Here is the abstract you requested from the nano_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D Integration with High Performance Coaxial Through Silicon Via (TSV)|
|Keywords: Coaxial TSV, 3D Integration, Fabrication|
|3D integration is an enabling technology increasing packaging efficiency and density. This new and exciting technology also helps to overcome Moore’s law by increasing circuit density without scaling CMOS technology nodes. Two areas of interest are standard TSV integration for logic and low frequency applications, and high frequency applications where power losses must be managed. Current 3D TSV technology is constrained by power loss issues that limit signal integrity performance up to device speeds of 30GHz. 3D integration utilizing coaxial through silicon vias (TSV) is gaining considerable interest due to the superior high frequency performance compared to standard 3D interconnects. In contrast to standard TSV structures, coaxial 3D interconnects require more processing to integrate the metal ground shield that surrounds the copper via. This research demonstrates a low cost fabrication method for integrating coaxial TSVs within the confines of a standard CMOS process. The fabrication method for the coaxial TSVs allows for a 20% improvement in power loss compared to standard TSVs without ground shields. Due to the superior performance at high frequency these interconnects are ideal for the next generation of high frequency RF and millimeter wave interconnect and packaging applications.|
|Stephen Adamshick, Graduate Student
College of Nanoscale Science and Engineering, University at Albany, SUNY
Albany, New York