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Standard Measurement Methods for Enabling 3D Stacked Integrated Circuits
Keywords: measurement, 3d, integrated circuits
This talk will describe standard measurement methods being developed with the leadership of SEMATECH's 3D Enablement Center. These standards will accelerate the adoption of three-dimensional stacked integrated circuits (3DS-ICs) by providing the tools to measure wafers, wafer stacks, and chip stacks unique to the 3DS-IC environment. 3DS-ICs are expected to lead to improved density, power consumption and performance as the first generations enter high-volume manufacturing. They also hold promise as enablers of heterogeneous integration in future years. This talk will focus on two particular standards for which multiple-laboratory experiments are currently underway. The first is inspection and characterization of voids between bonded wafers. Wafer bonding in a 3DS-IC process is typically an intermediate step. After bonding, one or both of the wafers will undergo processes such as thinning, thin film deposition, lithography, and patterning. The presence of voids between the wafers will cause significant stack thickness variation, which can lead to failure at one or more of these steps. A number of tools can be used to characterize voids; this standard will provide members of the 3DS-IC community with guidance for choosing the tool or tools that will best address the specific need. The second standard is thin wafer handling. Since many advanced 3DS-IC processes will depend on wafers sourced from multiple fabrication lines (logic, memory, MEMS, optoelectronic), the actual 3D stacking will take place at a third-party entity, such as an outsourced test and assembly (OSAT) provider. This process flow makes it likely that wafers which have been thinned at the fabrication site will then be shipped to the OSAT. Experiments have been performed on a number of different shipping configurations using a standard drop test, supported by finite element modeling. The thin wafer shipping standard will provide the community with guidance for choosing the correct methods for successfully shipping thin wafers.
Richard A. Allen, Assignee to 3D Enablement Center
NIST/SEMATECH
Albany, NY
USA


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