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Thermal performance enhancement of glass interposers with copper vias similar to silicon substrates
Keywords: Glass interposer, Through Package Via, Thermal design
Silicon interposer-based packaging technology is being developed to replace organic substrates, which are limited in number of I/Os, and thermal performance. However, such silicon interposers face a number of fundamental and engineering challenges, such as high electrical loss, and high cost of interposer fabrication. Glass interposers offer many advantages over organics and silicon interposers, including ultra-high resistivity and loss, and lower cost at both raw material and processed interposer levels. However, it has two fundamental limitations; brittleness and relatively low thermal conductivity (~1 W/mK), compared to Si (~150 W/mK). This paper addresses the thermal challenge and demonstrates glass interposer to be similar in thermal properties to that of Silicon. Georgia Tech Packaging Research Center (GT PRC) with its industry partners has demonstrated high density of copper package through vias (TPVs) at low cost [1]. Large number of copper TPVs can be used, therefore not only for electrical but also to increase the effective thermal conductivity of the interposer due to the high thermal conductivity of copper (~400 W/mK) [2]. A modeling study was conducted to compare the thermal performance of glass interposer with different numbers of copper TPVs. To compare thermal performance of glass and silicon interposer, a mobile system application of interposer was considered. 2.5D glass and silicon interposers (25 mm x 25 mm x 200 µm) with a logic IC at 0.8W and a memory chip at 0.2W, mounted side by side, were modeled under different thermal paths. For more accurate simulation, thermal conductivity of polymer was determined experimentally and effective in-plane and out-of-plane thermal conductivities of glass interposer were used for computational efficiency. To apply realistic number of ground I/O and signal I/O vias, die area was separated into two regions. The peripheral region was modeled as a signal I/O area, connected only to an interposer, while the center region was modeled to have ground I/O vias corresponding to 20% of total TPVs. Ground vias were assumed to be connected to a thin copper layer (~20µm) embedded in the PCB, and different number of ground vias were used to study the effect of copper vias on thermal performance. The comparison showed that by incorporating copper TPVs as thermal vias, the junction temperature of the glass interposer decreased by 60%, while that of silicon interposer decreased by 45% compared to the interposer structures without TPVs, making both temperatures fall in acceptable range. Heat dissipation through the TPVs in glass interposer was more effective due to better thermal isolation between the logic and memory chips caused by low thermal conductivity of glass. Thermal isolation effect was also confirmed by comparing temperature changes at both interposers. Although there were differences in heat generation between logic and memory chips, temperatures of logic and memory at silicon interposer showed only 1~2 ℃ difference, while a 10~ 20 ℃ difference was found for the glass interposer. Effect of copper vias on thermal performance of glass interposer will be validated experimentally by comparing junction temperature of glass substrate with different number of vias.
Sangbeom Cho,
Georgia Institute of Technology
Atlanta, Georgia
USA


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