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A 256 kb (32kx8) EEPROM for >200 C Applications
Keywords: EEPROM, retention, temperature
Dennis Adams1, Randall Lewis1, Jason O’Brien1, Bill Hand1, Greg Marsh1, Ian Manwaring3, Donald Pierce2, Cory Sherman1, Sze Wong1 December 19, 2013 A memory retention study was performed on the W28C256 32kx8 EEPROM device to assess its suitability for use in high temperature applications above 200 °C. This study indicates this device has memory retention well in excess of 10 years at 225 °C. During 2014, characterization and extended life testing is planned to further assess device reliability for high temperature applications. The Northrop Grumman W28C256 32kx8 EEPROM is a radiation hardened device that has been successfully used in space applications since 1995. Nonvolatility is achieved using SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) charge storage technology. This design utilizes a four transistor memory cell (compared to a two transistor memory cell used in the W28C0108 128kx8 EEPROM). The objective of this study was to evaluate whether the four transistor memory cell and increased programming voltage (10 V vs 7.5 V for the 128kx8 device) would lead to improved high temperature memory retention. Cumulative time to retention failure distributions were generated by programming devices with a checkerboard pattern, followed by unbiased exposure to high temperatures, with interval retention testing at room temperature. Sample sizes varied from 14 to 33 parts. The failure criterion was defined as a single bit failure in a device memory. The activation energy was then derived based on traditional Arrhenius relationship for median time to failure (MTTF); MTTF = A*exp(Ea/kT) where Ea is activation energy, k= Boltzman’s constant and T= temperature The MTTFs measured were 1.6 days, 6 days and >42 days at 375, 350 and 300 °C, respectively (no failures were seen out to 42 days at 300 °C and testing was suspended). From these data, the thermal activation energy for memory retention was calculated to be 2.27 eV. Estimated retention life time at +225 C was 410 years. From this work, a wafer level screen was established to remove devices from the population that do not meet established retention requirements for >200 °C applications Fixturing is currently being built to allow electrical characterization of this device up to 300 °C. Accelerated life testing at 250 °C will be performed in 2014. A study is also planned to assess memory retention when devices are programmed at elevated temperatures for in situ reprogrammability. 1 – Northrop Grumman Corporation (Baltimore, MD) 2 – Sandia Technologies Incorporated (Albuquerque, NM) 3 – Rochester Institute of Technology (Rochester, NY)
Dennis A. Adams, Senior Consulting Engineer
Northrop Grumman Corporation
Linthicum, MD

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