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High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology
Keywords: High Temperature, SOI CMOS, 0.35 micron
Silicon-on-Insulator is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. In this paper we present a next generation high temperature SOI CMOS technology. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital domain, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper. Tests have been performed successfully up to 300°C. Due to the decreased feature size, especially integrated systems featuring large digital parts benefit from this technology. Systems on chip become feasible at a reasonable die size.
Holger Kappert,
Fraunhofer Institute for Microelectronic Circuits and Systems IMS

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