Micross

Abstract Preview

Here is the abstract you requested from the hitec_2014 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Design and manufacturing of a double-side cooled, SiC based, high temperature inverter leg
Keywords: Power electronics, silicon carbide, silver sintering
In this paper, we present a small (25x25x3mm3) power modules that integrates two silicon-carbide (SiC) JFETs to form an inverter leg. This module has a sandwich structure, i.e. the power devices are placed between two ceramic substrates, allowing for heat extraction from both sides of the dies. All interconnects are made by silver sintering, which offers a very high temperature capability (the melting point of pure silver being 961C). The encapsulation of the module relies on Parylene-HT, a dielectric material that can sustain more than 300C. The outline of the paper is as follows: -I) Introduction -II) Presentation of the sandwich structure: circuit layout, design considerations, selection and high-temperature test of SiC devices. 1200V SiC JFETs (SiCED/Infineon) are chosen because they can operate at more than 300C. All materials and processes are selected to achieve high temperature capability. -III) Sensitivity to silver migration: silver is known to migrate in the presence of high temperature, oxygen (or moisture) and electric field, forming conductive filaments that can cause short circuits. We present test results that confirm this issue, but we also demonstrate that parylene HT is a very efficient mitigation solution (10 times longer operating life before a short circuit occurs, compatibility with 3D structures). Tests were performed for 1000h at temperatures ranging from 250 to 350C, with more than 100 samples tested in total. -IV) Manufacturing aspects: first processing the commercial SiC dies to obtain silver-finished topside contacts instead of aluminium. Layers of titanium and silver are deposited through a metal stencil on the dies. The stencil has pockets to locate the dies and ensure alignment. Then we describe a 2-level etching of the ceramic substrates (DBC) to form features that match the pattern of the dies. This is a critical step, as the SiC JFETs have a very small gate pad (320x520um2). A specific etching technique was developed to achieve a 50um resolution, even when processing very thick (300um) copper layers. For the assembly (silver sintering process as well as alignment jigs), we use a micron-scale-based silver paste silver particles (Heraeus). A low pressure is applied on the assembly (2MPa to ensure good sintering without submitting the dies to excessive stress. Finally we describe the parylene coating, with a presentation of a cross section that shows the uniform thickness of the coating, even in the most intricate areas of the module. -V) Electrical characterization, which shows that the module is fully functional -VI) Conclusion
Cyril BUTTAY, Researcher
Laboratoire Ampere, CNRS UMR 5005
Villeurbanne, --
France


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems