Here is the abstract you requested from the hitec_2014 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|500kHz-5MHz Phase-Locked Loops in High-Temperature Silicon Carbide CMOS|
|Keywords: Silicon Carbide, Integrated Circuits, Phase-Locked Loops|
|Silicon Carbide (SiC) integrated circuits processes show promise for improved performance in high temperature, high radiation, and other extreme environments. All SiC IC processes technology to date areis in development, and presenting unique design challenges over more stable, mature Si processes. The circuits described are the first implementations of phase-locked or delay-locked loops in SiC. The PLLs are standard charge-pump topologies including a fully integrated passive loop filter. Two versions are described, one using a standard Phase-Frequency Detector (PFD) suitable for clock buffering and jitter reduction, and the other using a Hogge PFD suitable for clock-recovery from Non-Return-to-Zero (NRZ) serial data. These circuits are designed for operation up to 300℃. The designed frequency range of the PLLs covers the expected operating frequency capability of digital circuits in the current iteration of the process used. Current compact models are designed with Silicon in mind, and do not yet predict effects such as temperature scaling and back-body induced threshold shift well in SiC. Design methods utilizing “binned” models and circuit topologies were selected to optimize operate in regions with better model fitsdelity. This process offers a P-well in N-Substrate, in contrasting with many popular Si processes, which offer an N-well in P-substrate. NFETs can be body-source tied, but PFETs will always have body-supply ties. To avoid threshold shiftback-body effects, all logic is implemented using NAND gates, which have no series PFETs. The charge pump and voltage-controlled oscillator (VCO) are also designed without series PFETs. The VCO topology utilizes devices operating as current sources, charging explicit (non-parasitic) capacitors. This minimizes the variation in current through matched devices and avoids unequal device-aging effects. It also offers the maximum small-signal gain and allows for control of the operating frequency through a well-defined slew rate. This mode of operation reduces the effect of process uncertainty at the expense of a reduced power supply rejection ratio. Experimental results of both components and the system are presented. The tuning range, jitter/phase noise, frequency push, and operational lifetime at high temperature are shown for the VCO. Operation of both PLLs at 1MHz is demonstrated through both simulation and data captured from fabricated circuits.|
|Paul D Shepherd, PhD Candidate
University of Arkansas