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Zero stress die-attach” for wide band gap semiconductor power devices
Keywords: die attach, high temperature reliability, wide bandgap power device
Electronic packaging materials and processes are facing to a drastic change for the emerging power devices using post-silicon wide band-gap semiconductors like SiC and GaN. The key issue is the high operation-temperature over 200C that allows the power modules applied to mobile vehicles or heavy industries without special cooling systems. All the materials of packaging must be changed to meet the harsh environment of the high temperature. Thus, substrate materials, die-attach methods, various levels of interconnections, and molding/shielding should be revised at a viewpoint of total device design for high temperature reliability. One of the most critical assembling technique in the issue is die attach that maintains the thermal and electrical contact between semiconductor chips and metal/insulator substrates. These two classes of materials exhibit intrinsic difference in their coefficients of thermal expansion (CTE), Young modulus/softness, and thermal conductivity. Especially, the large CTE mismatch leads to concentrated thermal stress at the die to substrate interface when the device is exposed to a large temperature change from room temperature to the high operation-temperature. The thermal stress is actually the major source of failures in high-temperature devices, and hence, the joining structure should be designed for stress relaxation. As it has the largest area at contacts between semiconductors and substrate parts, die-attach requires the first precedence in the device packaging design for high-temperature resistance. High-temperature die-attach process in future needs to be lead-free as well. This is another driving force toward a new die-attach process of power devices. Many die-attach materials and processes have been proposed in the last decade, aiming to replace Sn-Pb high-temperature solder. In the present paper, we will review the elemental technologies for ultra-high temperature packaging, on the basis of the studies proposed by the authors’ group in the field. Basic but most promising method would be Ag paste sintering and Ag thin film bonding proposed as "Zero stress die-attach", which enables the fabrication of highly reliable devises with low pressure and low temperature. The authors have proposed the Ag micron-size flake paste hybridized with Ag submicron particles. The sintered Ag paste exhibits a homogeneous micro-porous structure ideal for stress relaxation, with keeping the high heat and electrical conductivities as well as structural rigidity. In our study, Ag flake pastes with low temperature sintering around at 200-250C is explored, and examined under thermal cycles from -50 to 250C. The bonded structure survives up to 500 cycles without degradation, and keeps more than 50% of the original strength after 1000 cycles. The authors also presents the Ag/Cu flake pastes with or without the photo-sintering process of these pastes. The direct bonding method using Ag or Cu thin-films are also promising die-attach method at low pressure/temperature. By this method, the thin film layer forms a perfect bond line without any significant void even at 250C under little pressure. High-temperature solder of pure Zn are also proposed as another choice especially for cost-performance. Zn possesses the excellent electric and heat conductivities. Improvements in the mechanical and chemical properties of Zn solder can be achieve by a trace amount of metal additives. Thus, in the series of research on the next-generation die-attach technology, we would propose a design guidance for ultra-high temperature packaging for wide band gap semiconductor power devices by the "Zero stress die-attach".
Katsuaki Suganuma, Professor
ISIR, Osaka University
Ibaraki, Osaka

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