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New Era for Highly-integrated, Highly-reliable, Miniaturized and Low-cost Packaging
Keywords: Packaging, Future, Past
Semiconductor and systems landscape is changing dramatically. ICs, on one hand, for the most part, are becoming commodities, providing much lower profit margins than ever before, leading to industry consolidation to less than five companies within 10 years, worldwide. The driving engines for electronic systems, on the other hand, are also changing dramatically to Smartphones and Tablets, requiring an entirely different IC, package and systems vision than before – ultra-miniaturization, ultra-high heterogeneous functionality at ultra-low cost. This is more than Moore's Law, lot More than Moore's Law (MTM). It is System-Level Moore's Law (SLM). The packaging so far has been 'packaging of individual devices.' But the new smart systems electronics era needs to be 'packaging of highly integrated sub-systems and systems.' Any package vision must address and accommodate this changing landscape both in ICs and systems, to act as a bridge between homogeneous and heterogeneous devices, adding value to these devices, and contributing to miniaturization of highly-functional systems such as Smartphones which promise to perform every imaginable function that almost everybody wants and can afford. At device level, the new packaging must enable superior multiple devices including split SOCs in 2D and 3D, thus extending Moore's Law in 3D; and at system level, the new packaging must enable 'heterogeneous systems providing such functions as digital, wireless, analog, sensors, wireless healthcare, and many others – all in a thickness of less than 6000 micron.' In contrast to the old era, with a singular focus on 'Transistor Scaling' to form ICs and packaging of these ICs, the new era needs a new technology frontier referred to as 'System Scaling.' This new vision is very different from old. It brings synergy and vertical integration between advanced ICs, packaging of these advanced stacked ICs in 3D with TSVs in logic and memory devices, interconnected on ultra-high density and low-cost 3D interposer packages with their own through-package-vias (TPVs) to stack functional layers on both sides, to form ultra-miniaturized system boards called system interposers.
Rao Tummala, Director
Georgia Tech 3D Systems Packaging Research Center (PRC)
Atlanta, GA

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