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Advances in Leadless Lead-frame Processes for Extremely Thin and High Density Applications
Keywords: Leadless, Lead-Frame, High Density Packaging
'Leadless-lead-frame processes will realize substantial growth throughout our forecast period, as low-cost/enhanced-performance alternatives to the quad flat package (QFP) and small outline integrated circuit (SOIC) technologies. In 2014, leadless-lead-frame packages will be the largest packaging segment, on a unit basis, surpassing the SOIC.' Source Gartner's Jim Walker and Mark Stromberg: 'Forecast: Semiconductor Package Unit Demand, Worldwide 2H13 Update' This paper will summarize advancements in leadless lead-frame processes to provide extremely thin and high density package configurations leveraging robust QFN platform technologies. Demand for leadless lead-frame packages are forecasted to exceed one billion units per week with demand coming in a diverse range of end applications and device types representing a diverse range of package features and configurations. -- Automotive applications require advancements in leadless plating processes for improved solder joint integrity, while under the hood and other harsh environment systems require higher operating temperature performance. -- With over a billion Smartphones sold annually to an increasing range of cost / performance segments, handset designs demand an expanding range of unique requirements including: --- Total package mounted heights well below 0.5mm to enable thinner / lighter handsets with dense double sided PCB assembly. --- Increased lead density from dual row to full array leadless lead-frame configurations to deliver more I/O in smaller QFN configurations. --- Higher interconnect flexibility for both 1st level (complex bond diagrams including for stacked die) or 2nd level lead configurations for improved power, thermal or electrical performance. This paper will summarize advancements UTAC has made in assembly process and materials technology to develop new leadless lead-frame packages that address the wide range of application requirements. The paper will discuss advancements in: -- Lead-frame carrier design and process flow -- Thin die processing and die attach films. -- Fine pitch / low loop wirebond and flip chip interconnection. -- Vacuum molding -- Insulation molding of routing traces and lead-frame features. -- Post assembly copper carrier etching into final lead configurations. -- Solder print and ball attach options for lead array configurations. -- Saw singulation The paper will conclude with the benefits and applications that are adopting or well suited for this technology.
Lee Smith, V.P. Marketing
United Test & Assembly Center (UTAC)
Chandler, AZ
USA


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