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|Optimizing Solder Bonding for High Power Applications|
|Keywords: Optimizing Solder Bonding, High Power Application, Gold Tin Eutectic|
|In the late 1970’s, the development of high temperature solders was driven by the need to package high power Optical and RF devices based on the use of III-V compound semiconductor materials. As a consequence, AuSn eutectic soldering technology became commercially available in the mid 1980’s. The telecom and optoelectronic industries were the first to adopt AuSn for use as a high temperature die attach material. A decade later the U.S. defense industry started using high temperature/thermal conductive solders for assembling high power RF components based on GaAs, GaN, and SiC technologies. Northrop Grumman has been successfully making high power devices for several years, yet as transistor power requirements increase, improvements in heat transfer have become a critical part of the reliability equation. Properties such as higher eutectic temperature, low creep resistance, and higher reliability makes AuSn the preferred solder over SnPb, particularly at higher operating temperatures. Although the technology is mature, IC assembly manufacturing has been plagued by low yields arising from issues such as poor solder flow, excessive voids, and heterogeneous phase distribution. Several backside metal contacts have been evaluated to improve the Gold-Silicon (AuSi) eutectic solder joint. Minimizing solder voids is essential for thermal management and reliability improvement. Northrop Grumman has developed barrier metallization that reduces the number of voids by over 30%. MIL Standards cannot be used for hard solders such as AuSn and AuSi and therefore, diagnostic methods such as die shear and cross section analysis have been used to establish the quality of the solder joint. We hypothesize that the voids are formed by the localized freezing of the solder with the root cause a function of impurities and process variability. During this investigation, several barrier metals have been deposited at the backside of Silicon Carbide die. Analysis of the solder interface has been performed using die shear, Scanning Acoustic Microscopy, and IR thermal imaging. The investigation results have provided process improvements that increase die shear strength by 45% and reduce voids by over 30%. In this presentation, we will present identified root causes of die attach failure and review results from improved manufacturing processes.|
|Ramesh Varma, Consulting Engineer
Northrop Grumman Corporation