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|Mapping Chip-Package-System Thermal Crosstalk Effects|
|Keywords: In-Package Memory, Thermal Crosstalk, Thermal Simulation|
|Never before have the effects of thermal crosstalk been more evident than in System-in-Package (SiP) and In-Package Memory (IPM) products. Recently, these particular memory products are battling similar thermal engineering issues as microprocessor products have done for years. Having a combination of relatively low power DRAM chips coupled with a memory controller chip in a single SiP component presents several challenges. We would like to provide some insight into the thermal crosstalk scenarios that exist throughout the die, package, and system development stages. As such this work is not only beneficial for package and electronics cooling solutions engineering, but it is also important to die circuit designers and system architects in their conflict against hotspots in such heterogeneous semiconductor products. DIE-LEVEL EFFECTS In order to meet the density and capacity of leading edge SiP products, multiple chips and device technologies are required. As a result, very thin silicon die are used as opposed to standard flip chip die thickness used in System-on-Chip (SoC) solutions. In order to meet density and bandwidth requirements, these silicon die must be thin (<75um). It is well known that silicon thickness acts as a low-pass filter for heat transfer. Below a critical die thickness (~85um), heat travels in a vertical direction only with very little heat spreading [Estessam-Yazdani, 2008]. PACKAGE-LEVEL EFFECTS Thermal testing and Finite Element Analysis (FEA) simulation studies perform the maximum benefit in the early to intermediate stages of package and process development. At this stage there is a high degree of freedom (and opportunity), to explore different package options and designs. Based on an initial package form factor estimates, design parameters can be investigated as to influence on die temperature may include 3DI interconnections, package substrate, interfacial resistances, die stack shape, internal and external cooling solutions. In many instances, the use of step- or conformal-shaped metal lids has been instrumental in extracting the heat directly at the regions of high power density [Sikka, 2012]. The strategically positioned lid was be validated using was 3D thermal test vehicle packages. In addition, its thermal advantage over standard lid 3D packages was experimentally demonstrated and will discussed. SYSTEM-LEVEL EFFECTS Traditionally, discrete (or standalone) components can usually be adequately handled with respect to a thermal cooling solution (e.g., combination of heat sink, heat pipes, and/or a vapor chamber). Thermal crosstalk at a package- and system-level is less of an issue with discrete components. Current electronics packaging trends demand even more compaction of components from both physical floor planning and an electrical performance perspective. The sharing of a system-level thermal solution among several components with varying power dissipations requires a real and measurable challenge of thermal crosstalk. A series of system-level simulations will be highlighted to expose thermal engineering challenges for these various product solutions.|
|Steven Groothuis, Package Technologist
Micron Technology, Inc.