Here is the abstract you requested from the wirebonding_2014 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|The Future of Packaging - The Relevance of Wire Bonding|
|Keywords: Wire Bonding, Consumer Electronics, Semiconductors|
|Performance and Cost Consumer electronics is that main engine for growth in the electronics industry. We consumers have an insatiable appetite for features which require performance at low power, but only if they come at a low enough cost. Performance requirements drive increased chip complexity, which lead to rising design costs, resulting in few new market entrants and industry consolidation. The competitive need for innovative solutions and faster payback results in rising costs for R&D. Greater package complexity also results in increased manufacturing costs, which lead to continued progression of manufacturing outsourcing. This is all in the context of the volatile global economy that requires careful inventory management to control costs. Packaging Trends – Moore than Moore Advancements in electronic packaging performance and cost have historically been driven by higher integration primarily provided by wafer FAB node shrinks that have followed the well-known Moore’s law. However, the tremendously increasing cost of building new FABs will soon cause the performance/cost improvements achieved by moving to smaller technology nodes to become negative . This has initiated the idea of More-than-Moore and vigorous R&D for greater performance through packaging. Substantial performance improvements have been realized through wire bonded stacked die and stacked package-on-package technologies. On the cost side, the recent revolution in the use of copper wire bonding to replace gold has significantly reduced packaging costs. Now new highly integrated heterogeneous 2.5D packages with interposers and 3D packages containing through silicon vias have been developed, coupling memory and logic more closely. This enables bandwidth gains at reduced power by reducing package impedance. While these configurations greatly improve performance at lower power, the cost has not yet been addressed adequately. There is a lot of attention being given to the development of these new packages, but they are only going to be used for packages that absolutely require the increased performance they deliver because of their increased cost. Semiconductor Market Trends and How They Affect Package Development The market for semiconductors can be segmented into the categories smartphones, tablets, notebooks and PCs, network servers and storage, automotive, and all other. All of these segments are predicted to grow with Smartphones leading with a revenue CAGR of at least 16% over the next few years. Yet even this is misleading, unit growth is much higher topping 25%. Therefore when considering the highest volume packages, smart phones lead the way and this warrants a closer examination of the packages inside of them So what drives 3D packaging in Smart Phones? One summary from Samsung states that the answer to this question is higher density for the same footprint, higher performance / wider bandwidth, lower power consumption and heterogeneous integration. Now packaging solutions must strive to accomplish all of these. There is a lot of focus on the developments for 3D packages to accomplish these attributes, but if you look at the contents of a smart phone most of the chips are wire bonded? The chips that are the focus of 3D development are only the applications processor and the associated memory and the baseband processor. In this presentation I will describe the roadmap for these chips and show the market projections for flip chip and wire bond packages. One conclusion is that while there are definite requirements for higher performance packages there is also significant growth for wire bonded packages and that it will continue to be the dominant packaging technology for the foreseeable future.|
Kulicke & Soffa