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Tools for Thermal Analysis: Thermal Test Chips
Keywords: test chip, Analysis, tools
INTRODUCTION Irrespective of if a device gets smaller, larger, hotter or cooler, some method is needed to determine the thermal behavior of a given chip/package/heatsink configuration. This is typically achieved by a combination of models and measurements and is useful in guiding the design team to the most cost-effective and reliable package and cooling solution. Most production chips have few or no available connections for temperature sensing and require complex biasing schemes and clock signals to achieve maximum power dissipation. Although some live devices may be evaluated for thermal performance only the average junction temperature is reported and there is no indication of the spatial location of the temperature measurement. As we shrink feature size and combine more functions onto a given chip the problem of temperature distribution becomes critical. Now, and as we move into more integrated chip functionality, temperature gradients and ‘hot spots’ must be considered to evaluate thermal performance and reliability. Another scenario that is difficult or impossible using live die is to determine the junction temperature of chips in various locations in a multi-chip application. In stacked, SiP, 2.5 and 3D packaging the problem also includes measuring temperatures across the stack or array of chips.
Tom Tarter, CEO
Package Science Services
Santa Clara, CA

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