Here is the abstract you requested from the Additive_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Additive Manufacturing of 3-D Nanoscale Interconnects for Printed and Flexible Electronics|
|Keywords: Interconnects, Nanoscale Printing , Printed Electronics|
|Flexible electronics are lightweight, rugged, bendable, rollable, portable, and potentially foldable. Much work have been done to address the issues such as patterning and materials combinations to provide optimum performance of thin-film transistors (TFT) and p-i-n photodiodes for flat panel display and image sensor backplanes. However, fabrication of multilayered interconnects in these devices is still challenging. Conventional interconnect fabrication techniques such as electrodeposition and vacuum deposition require high temperature and pressure processing with excessive use of chemical additives, which makes them incompatible with plastics used in flexible electronics. There is a need for a room temperature and pressure-manufacturing method to create multilayered interconnects for flexible electronics. Herein, we introduce a new, material independent, room temperature and pressure manufacturing process for printing 3-D interconnects. In this process, colloidal nanoparticles (NPs) are precisely assembled and fused into 3-D nanostructures in a single step using an externally applied electric field. Compared to conventional fabrication methods, this method is carried out at room temperature and pressure without the need for an intermediate seed layer and chemical additives. This significantly reduces the cost and complexity associated with conventional manufacturing. In contrast to electroplating or thin film deposition, this method can fabricate solid nanostructures from inorganic or organic NPs made of conducting, semiconducting or insulating materials with feature sizes from several microns down to 25 nm, and do it in less than a minute over a large area (wafer scale). Using this technique, we have fabricated nanopillars made from Cu, W, Au, Si, SiO2 and their hybrid derivatives. TEM (transmission electron microscopy) and electrical characterizations reveal that manufactured metallic nanostructures have polycrystalline nature without any voids and very low resistivity (~10-7 Ω·m). This novel approach can find application in MCPs, MCMs, chip-on-board (COB), wafer-level packaging (WLP), flexible electronics, hybrid silicon to printed electronics attachment.|
|Cihan Yilmaz, Associate Research Scientist