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|Experimental Measurement and Theoretical Modeling of Inter-Die Thermal Resistance in a 3D IC|
|Keywords: semiconductor devices, thermal measurement, inter-die thermal resistance|
|Thermal modeling and temperature prediction in 3D ICs are important for improving performance and reliability. A number of numerical and analytical models have been developed for thermal analysis of 3D ICs. However, there is a relative lack of experimental work to determine key physical parameters in 3D IC thermal design. One such important key parameter is the inter-die thermal resistance between adjacent die bonded together. In this talk, a novel experimental technique to measure the inter-die thermal resistance of a two-die stack is presented which may be helpful in determining inter-die thermal resistance of other kinds of 3D ICs. The 3D IC used in this work is an unequally sized two-die stack consisting of a two unequally-sized die. Bottom die is 6.6 mm by 7.5 mm and top die is 4.1 mm by 3.6 mm which every die has 0.25 mm thickness. Each die contains an embedded heater and a resistance thermometry based temperature sensor. The experimental setup and model to measure inter-die thermal resistance are based on heating one die and measuring temperature rise in the other die in a short period of time to neglect boundary effects in the experimental setup. The temperature rise of every die measured by using high-speed data acquisition technique which performed by LabVIEW. This technique can be used to determine the inter-die thermal resistance between two die or thermal resistance of every die. A numerical model also developed to predict the temperature distribution in the same geometry with consideration of different amount of inter-die thermal resistance, then by comparing the experimental data with numerical simulation, the value of inter-die thermal resistance was found. A theoretical model has been developed to calculate the inter-die thermal resistance and the experimental data compared well with theoretical results. This work may be useful in determining the inter-die thermal resistance between adjacent die in 3D ICs and having better understanding of thermal transport in 3D ICs which leads to more thermal friendly design of new generation of 3D ICs.|
|Leila Choobineh, Assistant professor
SUNY Polytechnic Institute