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Challenges for Next Generation Packaging
Keywords: Double side plating , pillar plating in flip chip , electroplating
As device geometries continue to shrink, semiconductor packaging technologies face continuous challenges to remain relevant and economically viable. Pressure on the entire supply chain is mounting and the drivers are clear – enhanced performance, more functionality, and reduced costs. The limitations of Moore’s law are well known and advanced technology nodes are no longer providing a significant cost reduction. Investments in next generation node technologies are perhaps too substantial and precarious and thus, the industry is turning to advanced packaging to enable improved performance and functionality, following the “More than Moore” approach. While it is still unclear which of the advanced packaging technologies offer the best performance at the lowest cost, it is critical that companies actively engage and examine the variety of options, as opportunity costs are significant. Accordingly, there are a great number of R&D assessments being undertaken, using a variety of packaging applications, for example fan out wafer level packaging, flip chip, wafer level chip sized package, embedding dies, among many others. One key challenge for packaging researchers and manufacturers is to develop technologies that are innovative, aligned with market trends and future requirements, and of course profitable, all while minimizing opportunity costs. Thus, there is an urgent need to develop innovative technologies to satisfy the future challenges for advanced packaging and that also cost effectively address the emerging requirements. This paper/presentation will discuss some of the key challenges in advanced packaging and how they can be overcome with a novel approach to electroplating. Embedding components in power chips For assembly technologies in power chips, embedding dies has been identified as a promising solution for enhancing performance and reducing manufacturing costs. Embedding dies refers to the integration of components (passive components and integrated circuits) within the layers of a die package. Market research on embedded active and passive dies demonstrates that this technology will witness wide acceptance in the coming years, particularly for mobile and automotive applications. Substrates with embedded dies offer smallest form factor and footprint, as the die package is significantly denser and therefore takes up less space on the PCB or IC substrate. Moreover, the process sequence, and in particular the number of plating steps, is shortened when dies are embedded and electroplated on both sides. There are a number of other benefits of embedding dies, including higher levels of integration and improved thermal and electrical performance. Embedding dies facilitates a shorter electrical path, which results in a faster signal and overall electrical performance for the entire package. Embedding dies also presents the opportunity for increased levels of integration and the ability to house multiple dies, of various functionalities, in a single package. Typically, during the embedding process, RDLs and backside metallization are done by sputtering and plating each side of the wafer or panel individually. This is a costly and equipment intensive exercise that can also slow down the production flow. Advanced Cu deposition will continue to be a mainstay in advanced packaging, but not without some limitations. A primary concern regarding Cu deposition is the fact that as the substrate thickness decreases and thicker Cu RDL layers are required (in FOWLP, for example), warpage is a critical processing challenge. Double side plating – which refers to the simultaneous plating on both wafer/ panel sides - is able to overcome the warpage which is typical in high end processing with stress compensation achieved by simultaneous Cu depositions. The advantage here is significant, as warpage has a major impact on yield. Yield is also a challenge for panel-based manufacturing of embedded components. Notwithstanding, high volume manufacturers have already adopted embedded technologies for low I/O dies on panel-level. Fan out wafer/panel level packaging One example of embedding dies is fan out wafer/panel level packaging. Fan out is a preferred packaging approach as it is designed to considerably increase I/O density with a reduced footprint and profile, partly due to the fact that it’s thinner than flip chip, as it does not require a package substrate. Warpage is a critical processing challenge in fan out due to the use of thinner substrates and thicker Cu depositions. Yet another challenge is posed due to the lack of infrastructure. Both the equipment and complete fabs are unable to handle thin wafers and panel format, while continuing to provide desired yield. Fan out processing may soon be done on panel level, as the price per piece significantly decreases from larger wafer sizes to panel. However, standard panel tools are not designed for processing wafers and tend to have a significantly lower yield than their wafer counterparts. This is partly due to the design of panel tools and the fact that they have not been engineered to satisfy the highest ISO standards. Atotech’s new ECD tool MultiPlate has a double side plating capability that enables simultaneous plating of vastly different structures on each wafer or panel side, such as large pads for the back side metallization and fine lines of the RDL structures. MultiPlate is designed to satisfy the stringent requirements for next generation advanced packaging applications, both on wafer and panel level, and can also be customized according to the customers’ production requirements. With its double side plating capability, it also effectively addresses the warpage issues which are common with embedded components. High speed pillar plating in flip chip Traditional wire bonding is being surpassed by flip chip as the preferred packaging application for sub 45nm node technologies. Flip chip is technically superior to traditional wire bonding which requires a larger footprint and offers limited I/O density. More importantly, thermal and electrical performances are significantly improved with flip chip. For the most advanced technology nodes, the preferred interconnection technology in flip chip is Cu pillar. The standard process requirements for pillar plating include exceptional void performance, nonuniformity of less than 5 percent, and high current density plating at 10+ ampere per square decimeter (ASD). Each of these parameters contributes to the overall throughput, reliability performance, and yield for the plating process. Therefore, it is essential to develop a pillar plating technology that can deposit pure Cu with high deposition speed, without impacting the voiding performance and uniformity, both of which influence the electrical performance. Atotech’s unique MultiPlate in combination with their high purity chemistries satisfies all of the performance requirements for Cu pillar applications and provides a higher throughput than standard process of record, with a system throughput capacity of 50 wafers per hour. Using reverse pulse plating, the process is optimized to the desired pillar profile and shape, thereby reducing doming or dishing, and improving the overall uniformity of the deposited Cu (< 5 percent WIP/WID/WIW). In MultiPlate, deposition is significantly faster (≥20 ASD) than traditional fountain platers (≤10 ASD) and voiding performance is enhanced. Pure Cu depositions are made by possible by use of high purity chemistries and close monitoring of the bath components during plating. All of this is achievable because of the technically superior design of the system.
Cassandra Melvin, Application Engineer for Semiconductor Advanced Packaging
Atotech
,
USA


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