Here is the abstract you requested from the CPI_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Cost Reduced Far Back End of Line (FBEOL) for Advanced Si node (28/20/16nm) Lead free Chip packaging interaction (CPI)|
|Keywords: CPI, Lead free, ULK/ELK material|
|The introduction of extreme low-k (ELK)/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling-down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties of interlayer dielectric material (ILD).. Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate and lead free bumps. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate will transfer to the die through C4 bump. Reliability ULK/ELK flip chip package with lead free technology has received significant attention, especially in the area of ELK/ULK crack underneath the bump caused by chip-packaging interaction. A lot of efforts have been made to improve the CPI reliability. Most important solution is to increase the thickness of the last metal layer and apply Al metal to reduce the stress on the ULK/ELK material. But the consequence of this solution is to increase the wafer process cost and cycle time. In this paper, we proposed a cost reduced far back end of line (FBEOL) to reduce the wafer process cost and cycle time. FEA has been used to optimize the parameters of FBEOL structure of UBM size, passivation thickness, PI opening and thickness, Ni thickness and UBM undercut. Test TVs with 20X20 mm2 from 28nm/20nm/16nm Si technology have been used for the CPI qualification for each technology node. The reliability tests include quick thermal cycling test (QTC, -40 to 60°C), precon test (MSL3), TCG (-40 to 125°C), HTS (150°C) and UBHAST have been done to qualify cost reduced FBEOL. This cost reduced FBEOL has been in high volume production on AMD 28/20/16nm products.|