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|Assembly Solutions for Fan-Out Wafer Level Packaging|
|Keywords: fan-out, assembly methods, cost-of-ownership|
|Fan-out packaging is seeing widespread interest across a wide spectrum of device types and is emerging as an important and rapidly growing package. Within fan-out packaging there has been a proliferation of package types and assembly methodologies – face up/face down, die first/die last, single die/multi die with passives, POP, and a roadmap which extends wafer level to panel for certain applications. For each of these packages there are different assembly equipment requirements. This presentation will discuss and compare the assembly equipment’s technical requirements for die placement prior to reconstitution and challenges for various types of fan-out technologies. The key challenges for the die placement equipment focus on achieving initial placement accuracy requirements, placement compensation for die shift after mold, greatly differing force and temperature profiles for die placement depending on the process flow, mitigating the effects of chip warpage and carrier warpage, and architectures which allow for bonding die of various sizes as well as passives in one pass. Each assembly methodology also has different implications for potential stresses in the package. The features and special requirements for new die placement equipment will be discussed along with the throughput and cost of ownership that can be achieved for these emerging applications.|
|Bob Chylak, Global Vice President for Process Engineering
Kulicke and Soffa Industries, Inc.
Fort Washington, PA