Here is the abstract you requested from the CPI_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Assessment of Optimized Process Quality and Reliability for Wafer Level applcations.|
|Keywords: Chip Package Interaction, Wafer Level Fanout, Die Edge Delamination|
|Fanout Wafer Level Packaging (FoWLP) is a very attractive solution for microelectronics applications requiring optimized performance, smaller form factor, and low cost. By utilizing such an approach where system integration is done to multiple chips on a single package frame, the need to ensure much higher levels of process integrity, quality, and reliability becomes absolutely critical, especially if the total product volume lies in the range of tens of millions of units. A single defect type may negate the benefits of such an approach because the cost of losing one FoWLP unit results in the loss of multiple devices. Thus, yield, quality, and reliability optimization using such a package solution is critical for successful large scale manufacturing. In this talk, the issue of defectivity and its impact on quality and reliability on Wafer-Level (WL) devices with regards to the issue of Die Edge Delamination (DED) and Chip Mechanical Integrity (CMI) is discussed. Through this discussion and the resulting solutions found to improve WL quality and reliability, better understanding on how to assess the quality and reliability of a given FoWLP solution for large scale production will be demonstrated.|
|Ennis T. Ogawa, Quality and Reliability Engineering