KESTER

Abstract Preview

Here is the abstract you requested from the dpc_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

High-Yield Via-Last TSV Process by Notchless Silicon Etching and Wet Cleaning of the First Metal Layer
Keywords: 3D IC, TSV, via-last
Three-dimensional (3D) integration technology with through-silicon vias (TSVs) (1-3) has been developed as a key technology for realizing high-speed, very compact, and highly functional electronic systems. This technology has been used in high-performance field-programmable gate arrays and CMOS image sensors (4,5). To expand its application to various other systems (e.g., array sensors), high-density arrays of small TSVs must be formed through a low-cost, high-yield process. TSVs have typically been formed by the conventional via-middle or via-last process. In the via-middle TSV process, small TSVs can be easily formed by high-aspect-ratio Si etching, conformal deposition of an isolator, metal filling, and chemical mechanical polishing (CMP). However, the fabrication cost is high because a complex process is required to reveal TSVs from the backside of the wafer. On the other hand, the backside via-last TSV process is a simple and cost-effective approach, though it does have some drawbacks. Notching near the bottom corners of TSVs can cause large leakage current, and formation of the contact region between TSVs and the first metal layer is difficult when the TSVs are small. Here, we propose a high-yield via-last TSV process by notchless silicon etching and wet cleaning of the first metal layer. By this process, a high-density array of small TSVs (TSV diameter: 5-6 um; TSV depth: approximately 22-23 um; TSV pitch: 20 um; number of TSVs: 20,000) can be realized. The procedure is as follows. First, an 8-inch Si wafer is bonded to support glass and thinned to approximately 25 um by backgrinding and CMP. Then, photolithography is performed using an i-line stepper with an infrared camera. Next, Si deep etching is performed using SF6 gas and C4F8 gas, and SiO2 etching is performed using CHF3/O2 gas. By optimizing the etching conditions, notch size can be kept below 0.5 m. After the photoresist is removed, the TSV liner oxide is deposited by low-temperature plasma-enhanced chemical vapor deposition. Etchback is then performed to remove the oxide at the bottom of the TSVs, followed by wet cleaning of the first metal layer. This cleaning step is crucial for realizing high-yield fabrication because it removes contaminants on the first metal layer and creates good electrical contact between the TSVs and the first metal layer. Barrier and seed layers are deposited by ion sputtering, and Cu electroplating and CMP are performed. Finally, the backside redistribution layer is formed. Electrical measurements showed that the TSVs had good electrical characteristics. TSV resistance was below 0.1 ohm, TSV capacitance was approximately 43-67 fF, and leakage current between the Si substrate and a TSV was below 29 pA. In addition, the high TSV yield of 79% surpassed that of a previous study (6). These results demonstrate that the proposed via-last TSV process is effective for realizing high-performance 3D systems with a number of TSVs.
Naoya Watanabe,
National Institute of Advanced Industrial Science and Technology
Tsukuba, Ibaraki
JAPAN


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems