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|Cost Analysis of a Wet Etch TSV Reveal Process|
|Keywords: TSV, Cost Analysis, Wet Etch|
|Through silicon vias (TSVs) are a key design element within electronics packaging today. From a cost perspective, while it is generally true that TSVs should be avoided if any other packaging alternatives are available, there are more and more cases in which only a design utilizing TSVs will meet product requirements. When this occurs, every portion of the TSV Reveal process becomes a cost driver, and it is worthwhile to optimize the process and reduce cost in every step wherever possible. Veeco PSP has introduced a wet etch tool and process that reduces the number of steps and the cost of the TSV Reveal process. A SavanSys cost model was built to analyze both this process and the current industry baseline TSV Reveal method (dry etch). This paper discusses first, the overall TSV creation process, then the TSV Reveal process. The paper also provides a cost comparison between the current dry etch process and the TSV Reveal process. Key cost drivers are highlighted. A series of detailed cost trade-offs are considered to compare the two processes and test the sensitivities of the key variables. The impact of throughput (etch rate), equipment cost, material cost, and yield are evaluated. Activity-based cost modeling is used. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time, labor, cost of material (consumable and permanent), tooling costs, capital costs, and yield loss associated with the activity. The goal of this analysis is to understand the key cost drivers associated with the subset of steps related to TSV Reveal, as well as to analyze the TSV creation process as a whole.|
Veeco Precision Surface Processing