Abstract Preview

Here is the abstract you requested from the IMAPS_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Proposal of Ultra-fine and High Reliable Trench Wiring Process for Organic Interposer.
Keywords: Organic interposer, High insulation reliability, Photosensitive dielectric film
The organic interposer technology with ultra-fine line & space has been required in order to achieve high density interconnection between chips with low cost. Current organic substrates by SAP (Semi-Additive Plating) technology are limited to line & space larger than 8 μm because of the weak adhesion of Cu line and wire thinning during the seed etching. To solve the above technical issues, the trench wiring method has been studied. The trench wiring is made by laser abration of dielectric, spattering, Cu plating and then CMP. However the laser abration is difficult to achieve fine trench with smooth side wall and CMP is not suitable to substrate process because of high assembly cost. Another challenge is the insulation reliability because of the narrower insulator between wires and the thinner insulator between high density wiring layers. In this paper, we propose the low cost assembly process of ultra-fine wiring layer with 2 μm line & space showing high insulation reliability. In order to achieve the fine trench wiring, we have used 3 μm thick photosensitive dielectric film realizing 5, 3 and 2 μm line & space trench with smooth side wall. The surface planer method made 2 μm line & space trench pattern filled with Cu by spattering and plating planarized below 30 nm surface flatness (Ra). The Cu wiring surface was covered with the thin barrier metal layer by electroless plating, which is compatible with wafer as well as substrate processes, and the 3 μm thick photosensitive dielectric film. The wiring layer of 2 μm line & space provided by the proposed processes has passed the biased HAST (Highly Accelerated Stress Test) over 200 h. Next, we propose the organic interposer assembly with much lower cost. In addition to the above proposal, the sintered Cu paste has been applied to a seed layer instead of the spattering. To satisfy both low resistance of the sintered Cu and high adhesion to the insulator, the adhesive paste was filled into the Cu porous derived from the sintered Cu paste. The wiring layer of 10 μm line & space has passed the reliabilities such as MSL2, thermal cycling test and biased HAST.
Kazuyuki Mitsukura,
Hitachi Chemical
Tsukuba-shi, Ibaraki

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Rochester Electronics
  • Specialty Coating Systems
  • Spectrum Semiconductor Materials
  • Technic