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Effects of Silicon Wafer Bump Pad structures on Solder and Cu Pillar Flip-Chip Reliability
Keywords: bump pad design, modeling, reliability
Solder or Cu pillar flip-chip silicon die technology has been widely used in chip to package mobile module products. In early design phase designers usually apply standard bump design rules with top metal pad only during integrated circuitry (IC) die design due to lack of detail information of actual metal layer stack-up from the wafer foundry. However module reliability data showed that the stack-up and thickness of metal layers in a silicon die has a great effect on package stresses, especially for big size of Cu pillar flip chip die. In this paper, effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly on-line data were collected, analyzed and presented in this paper. The reliability and failure analysis were performed to verify the failure modes. A guidelines for designing solder and Cu Pillar Flip-chip bump pad structures has been developed and presented in this paper.
Shannon Pan, Package engineer
Greensboro, NC

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