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Overcoming Assembly challenges for low profile fcBGA PoP
Keywords: Assembly, fcPoP, Thin
Assembly processing challenges associated with a low profile fcBGA POP designed to accept a 0.4mm pitch 256 Ball DRAM package are highlighted. Routing two channel memory controller blocks on the base chip to line up with the fixed DRAM landing pad sites requires crossing one Address and Control signal set over the other. To address this crossing in the PoP controller chip, a thick layer copper RDL was deployed at the bump level to bring the signals in proximity to the DRAM’s JEDEC ball map. The 4-mask RDL/Cu-Pillar arrangement used for the “uncrossing” left a 10-13um of polyimide layer on the base die that presented die thinning and handling challenges for assembly. The 0.4mm DRAM memory package pitch used as TOP package dictated a very tight stand-off and therefore a very low profile controller chip. The extra polyimide required on the controller chip had significant impact on the handling of these thinned wafers and subsequent dies through the assembly process. Of course, some of the more recent package technologies like Amkor’s Thru-Mold Via (TMV) or Invensas’ Bond Via Array (BVA) meant for tighter DRAM pitches could have been used as solution without the need for a low thickness die. If it can be implemented the simpler bare die fcBGA PoP offers a simpler and more cost competitive approach. The process optimizations and techniques needed to extend the fcBGA capability to handle a 0.4mm pitch DRAM are covered in this paper. The paper will show that the traditional fcBGA can be pushed with proper material selection and process choices to provide a reliable base package to accept 0.4mm package in a PoP implementation – even in cases with substantial polyimide coverage
Abu Eghan, Sr Manager, Assembly & Packaging
Open Silicon
Milpitas , CA

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