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Enabling Low Warpage on Low-Profile BVA Package On Package (PoP)
Keywords: Low Profile BVA, Package On Package (PoP), Warpage
With an increasing demand to reduce package thickness and develop low profile components for mobile processors, the semiconductor industry is forced to consider thinner substrate and die options to reduce the total package thickness. The recent trends for Package-on-Package (PoP) configuration are demanding 1.0mm or less total height for the stacked processor and memory components. Bond-Via-Array (BVA) technology facilitates next-generation Package-on-Package (PoP) by utilizing wirebond technology to achieve fine-pitch interconnects at controlled height. With the thinner components in PoP, certain challenges such as warpage and reliability are posed towards accomplishing a high-yielding stacking process for both the base logic (SoC) and topside memory. Different substrate technologies also have significant contribution towards the warpage as we reduce the thickness of substrate. With the help of Finite Element Analysis (FEA) we study the impact of substrate thickness with different substrate technologies and key materials on BVA PoP warpage and stack height. Also, FEA is used to optimize mold material selection as well as mechanical aspects of thinner dies and substrate in order to minimize package warpage. This analysis is based on an industry standard package outline. A detailed analysis of results includes comparison of simulation data with measurements of actual samples with various materials and thicknesses. The FEA model is validated with prototype packages by measuring actual warpage as a function of temperature. Experimental data for exposed die and over-molded die samples are included in the completed results and analysis.
Akash Agrawal, Sr. Mechanical Simulation Engineer
Invensas Corporation
San Jose, CA
USA


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