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|High Selective Wet Silicon Etch Chemistry and Process for Advanced Semiconductor Packaging|
|Keywords: TSV, Wet Chemistry, Uniformity|
|In recent years, increased demands for thinner, lower power consumption, lower cost, and higher performance semiconductors for consumer electronic products have driven the semiconductor industry’s innovation. At the front end, feature size shrinks continuously following Moore Law, to today’s 14 nanometer technology . At the back end, 3D and wafer level packaging have been the focus. 3D Through-Silicon Via (TSV) and Fan Out Wafer Level Packaging (FOWLP) are two key technologies at the backend. These two enabling technologies reduce interconnect length to increase device speeds, and increase interconnect density to reduce the package form-factor. In via-first and via-mid TSV integration flows, Si wafers must be thinned from the backside to reveal the Cu for the wafer to make contact with another wafer or chips. Typically, this thinning is performed by grinding the back side of the wafer, polishing to remove the subsurface damage and to eliminate stress in the wafer, and then etching with a plasma or wet chemical process to reveal the Cu vias [2,3]. A similar silicon thinning/etch process is also involved in the FOWLP process integration flow. This paper will describe a wet silicon etch chemistry and a process as a simple and cost-effective alternative to the polish/plasma etch silicon thinning and/or removal process. The new etch chemistry improves Si etch rate over traditional etchants such as tetramethylammonium hydroxide (TMAH). The chemistry has very high silicon etch selectivity over SiO2 and copper films, with etch rate (ER) ratios greater than 5000 and 1000 respectively. Chemical compatibility with typical packaging materials such as polybenzoxazole (PBO) and polyimide (PI) will also be discussed. Last but not least, TMAH is not a component in the chosen chemistry because of safety concerns specifically related to TMAH toxicity. The process was developed using an industrial grade single-wafer process tool. This process uses an algorithm to control etch profiles to compensate for in-coming wafer thickness variations. Integration of wafer thickness measurements before and after etching–within the single-wafer equipment provides the high-accuracy process control needed for high-volume manufacturing. Improvement in surface roughness and etch uniformity are achieved with this wet process through the combination of chemistry performance and process optimization.|
|Yongqiang Lu, Director of Electronic Applications