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Smart in-line defectivity/metrology process control solution for advanced 3D integration
Keywords: microbump, automatic visual inspection, integrated metrology
The demand of smart devices for Internet of Things (IoT) applications is expected to increase exponentially [1], and 3D integration technology is one of the major candidates to allow flexibility and cost effective solutions for their fabrication. Despite the considerable improvement reached to industrialize the vertical stacking process that is the core of 3D integration, any reliable interconnection is still subject to challenges and unpredictable process variations [2]. Therefore, the need for process control solutions to provide quick root cause analysis to minimize the Mean-Time-To-Detection of fabrication problems is mandatory. In this context, searching surface defects and measuring their critical dimensions is of paramount importance. Recently, we could demonstrate that Automatic Visual Inspection/Classification (AVI) and in-line local metrology integrated into a unique platform was a valid solution to replace off-line characterization [3, 4]. However, the experience cumulated at CEA-Leti over two years pointed out that in-line metrology is still time consuming, and confidence in the results is sometimes deteriorated by the measured site’s morphology. To overcome the above mentioned limitations, for the first time we here demonstrate the key advantage of a smart integrated inspection/metrology approach, where 2D/3D characterization is driven by the results provided by AVI. This innovative in-line process control concept consists of detecting/classifying structural defects automatically on 100% of the wafer. In turn, local metrology is applied on “GOOD” targets only, according to quality criteria pre-defined by the user. Consequently, metrology accuracy is no more affected by the non-conformity of the measured site, and, even more important, the cumulated AVI/metrology processing time decreases since non-conformal sites are automatically removed from the metrology sampling plan. The smart logic can also be reversed, so as only defective sites are measured for either lateral CD or height, in order to characterize the impact of the defect. This is typically of help to discriminate between embedded or flat defects, that might not be critical when completing the vertical stacking, and protruding defects exceeding the height of the bumps, which must be avoided to establish any reliable electrical connection. As a case study, we applied the above mentioned smart logic to characterize the fabrication process of CuSnAg µbumps and CuNiAu µpillar (width 10µm, pitch 20µm) hosted on 300mm silicon wafers. After barrier/seed etch, we assembled these wafers by thermo-compression and we measured the electrical resistance of the daisy chain. We investigated this process from defectivity and metrology standpoints using a unique in-line platform (NSX® Series, Rudolph Technologies, Inc.) that combines AVI with metrology sensors. Results from AVI were used to trigger optical CD, interferometry and confocal line scanning only onto targets of interest. The results of the analysis forwarded to the etching systems to drive the following process step correctly. Moreover, we investigated the correlation of the CD/height information with the electrical measurements. Quantification of the inspection time revealed an increase in throughput of 30% on average, if the smart logic concept was used, while consistency of the automatic morphological accuracy was preserved, as confirmed by in-line mechanical profilometry.
Nicolas Devanciard, Metrology and Defectivity R&D Engineer
Grenoble, France

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