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The Mold + RDL structure on the high density substrate (i-THOP) for mobile application
Keywords: Panel-based Die integration, High performance package, package structure
The current trend in the electronics industry is one of increased computing performance, combined with a seemingly unending demand for portability and increased miniaturization; this is especially evident in the significant changes to the semiconductor device. With the efforts of semiconductor device manufacturing parties, Moore's law has been maintained for the past 40 years. Recently, Si node scaling is reaching critical physical limits mainly due to lithography processing. To overcome the limits, multiple patterning lithography steps were employed to achieve the required interconnect pitch reduction. These complicated process additions increase wafer fabrication cost significantly. To sustain the performance-improvement trend without increasing total cost, the partitioning of single die into a multi-chip architecture is widely studied in industry. These partitioned chips are then integrated into a single system-in-package (SiP). However, partitioning a single die into multiple split die causes two major challenges. The first is that it creates the need for very high density die to die (D2D) interconnection. This interconnection is needed to provide enough routing density between the multiple die. Based on design studies, it is believe that 2 micron line and 2 micron space is required in the package substrate. The second challenge is created by the increase in the overall die size. After partitioning the single die, each resulting smaller die must have its own IO circuits, and effectively increases the total die area. This increase is a penalty, as mobile devices have a limited package size. When comparing a conventional package on package (PoP), whose ballpitch to memory package is 0.4 or 0.5mm, to a die partitioned SiP, the SiP requires a finer pitch. This finer pitch is needed to have enough I/Os, but within a limited package size to support mobile devices. To overcome these challenges, the structure of i-THOP with POP pad, named "i-THOP with Mold+RDL structure", has been developed. Herein, i-THOP (integrated Thin film High density Organic Package) is a type of high-density substrate which was reported in 2013iMAPS. The term "Mold" is used to indicate the shape that the embedded die forms when using a high density filler resin. A key aspect to development of Mold+RDL is forming the multiple redistribution layers (RDL) over die and the fine pitch via connection. To achieve this, the proper material set was selected based on stress simulation and basic experiments. To develop the manufacturing process, a conventional printed-circuit board (PCB) production line was used to minimize production cost. This article reports the manufacturing and the quality results, including warpage and reliability test. The features of the tested sample are 1) D2D connection with 2 micron line, 2) multiple-chip mounting, 3) embedding chips by dielectric resin, and forming RDL, 4) connecting by 0.2mm pitch via between substrate and RDL. The conclusion is that we have demonstrated the feasibility of this structure successfully. Furthermore, we confirmed package robustness through reliability tests. The authors believe the i-THOP with Mold+RDL structure is a candidate for the next generation mobile application.
Masahiro Kyozuka,
Shinko Electric Industries Co., Ltd.
NAGANO-SHI, Nagano-Prefecture
Japan


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