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Novel glass wafer for minimizing thermal stress development during electronic device packaging process
Keywords: Glass career, thermal stress management, CTE controll
Recently, in high performance and efficient semiconductor packaging technology, there have been substantial advancements such as wafer level packaging (WLP) or panel level packaging (PLP). Glass can be utilized for support or career substrate in packaging process as it has excellent mechanical and optical properties. Specifically, it has high stiffness, high flatness, low roughness, small total thickness variation (TTV), high processability and high transmittance. However, in the case of large size packaging process, Si wafer or a reconstituted wafer integrated with glass substrate often shows an unneglectable warpage during thermal process. It is due to a constant of thermal expansion (CTE) mismatch between glass and other materials such as Si, mold compounds and wiring metals. To overcome this thermal stress issue, it is important to utilize glass wafers with carefully controlled CTE. The glass CTE is affected both by its composition and thermal history. Usually, the latter is influenced by the type of forming process. To control the glass CTE with high accuracy, we analyzed the effects and the temperature dependence of these factors quantitatively in detail. Then we developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on glass substrates whose CTEs are controlled in sub-ppm order and within the range of 4.0 ~ 12.0 ppm/OC, and glass substrate whose CTE is perfectly matched with Si. In the case of fan-out WLP (FOWLP) process, the warpage of reconstituted wafer with glass substrate and positional shifts of embedded dies are affected by various conditions such as Si/mold ratio, die geometries and distances to neighboring dies, and thickness of each layer. To minimize the warpage and positional shifts, we developed a series of glass substrates which have certain CTEs within the range of 4.0 ~ 12.0 ppm/OC, and it can be controlled in sub-ppm order. By selecting an appropriate glass substrate depending upon the reconstructing condition, the total wafer warpage and positional shifts of dies can be minimized. In addition, we have developed novel non-alkali glass substrate whose CTE is perfectly matched with Si throughout a wide temperature range. Although there have been several glasses that have a similar average CTE with Si for a certain temperature range, their CTE temperature dependences are quite different from that of Si. As a result of optimization of glass composition and production process tolerance, we have obtained the glass wafer whose CTE difference from Si is less than 0.02 ppm/OC at any temperature within the range from room temperature to 300 OC. Thus, it can minimize a thermal stress generated at the Si/glass interface regardless of the actual bonding temperature. This novel Si-CTE matching glass is useful for support substrate in Si back grinding process, and it can also be adopted as a substrate for through glass via (TGV) technology. In a final paper, we will show the experimental and simulation data of wafer warpage behavior in Si/glass bonding process and die molding process in FOWLP.
Shuhei Nomura,
Asahi Glass Co., Ltd.
Yokohama-shi, Kanagawa
USA


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