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Interposer based integration of chips with different integration technologies for high speed interfaces
Keywords: Interposer, Copper pillar, High speed
In this paper we show an approach for Interposer based integration of chips with different integration technologies for high speed interfaces. High speed interfaces means in this paper interfaces with more than 10 Ghz. Such interface needs well controlled interconnects between the involved chips. In the proposed approach two chips are involved there both has such interfaces with more than 10Ghz and talked together. The two chips are mounted onto an interposer. Well controlled interfaces means the whole path between the output from one chip to the input of the second path. This also includes the assembly technology of the two chips. In our case we have for the two different involved chips two different assembly technologies. One chip is assembled with copper pillars there as the other chips is mounted with micro balls. We shows in this paper who we can assembly the two chips with the different assembly technologies onto the interposer. We also shows how we can control the electrical properties for the different assembly technologies and also for the interposer interconntect. We also show how we can co-optimize the assumptions to the assembly technology (including the balls, the pillars, the pads, ) under consideration of the electrical and also the assembly domain. The co-optimization includes especially the dimensions of the pads, the balls, the pillars.
Andy Heinig,
Fraunhofer IIS/EAS
Dresden, Saxony

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