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Correlation of Through-silicon Via (TSV) Dimensions to TSV Stress and Reliability for 3D Interconnects
Keywords: TSV, scaling, extrusion
Through-silicon vias (TSVs) are a crucial technology for enabling full three dimensional integration, which will increase wiring density and improve package form factor. However, TSVs pose unique reliability risks, including thermal stress buildup due to the mismatch in the coefficient of thermal expansion between the silicon and the copper and the via extrusion phenomena, which can degrade device performance. Continued chip miniaturization requires that TSV dimensions be optimized, and it has been proposed that smaller TSV dimensions will eliminate negative stress effects. In this paper, the correlation of shrinking dimensions to TSV stress and reliability is investigated, focusing on the effect of the microstructure on the plasticity and extrusion for 10, 5, and 2 m diameter copper vias. The TSVs were all fabricated by the via middle process, and the 5 and 2 m diameter TSVs were fabricated by the same supplier with similar processing for improved study of the size effect. Synchrotron x-ray microdiffraction revealed local plasticity concentrated in the tops of the vias of all diameters, and showed that the TSV stress behavior seemed to depend on the variations in the grain structure. Electron backscatter diffraction quantified the microstructure to show a tight distribution of grain sizes after the post-plating anneal, but further annealing at 400C causing considerable data spreads for vias of all diameters. This result is consistent with the observed via extrusion statistics, in which the absolute values and variations in the extrusion heights increased significantly with further annealing. The wafer curvature technique is also used to observe the TSV stress relaxation behavior. Overall, these results suggest that scaling down TSV dimensions may not improve the stress and reliability behavior, particularly after further annealing at 400C. Since such annealing processes are required for via-middle fabrication, it seems that via reliability will continue to be a challenge as TSV scaling continues.
Laura Spinella, PhD Candidate
University of Texas at Austin
Austin, Texas
USA


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