Here is the abstract you requested from the IMAPS_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Process development and material characterization of Cu-Cu thermo-compression bonding (TCB) for high-conductivity electrical interconnects.|
|Keywords: Thermocompression bonding, Interface voiding, Material characterization|
|Die-to-package interconnects have not scaled in the last several decades and are generally in the 100 -200 μm pitch range, while in 3D integration die-to-die connections have been achieved at 40 μm pitch with some layout restrictions. The scaling of Interconnects to on-chip interconnect dimensions to the 2 μm pitch range using the CHIPS approach for heterogeneous integration remains challenging. In this study, we investigate the bonding techniques and materials issues. We focus on metal-metal Thermo-Compression Bonding (TCB) for realizing these interconnects. The popular metal choices include bare Cu, Cu plated with Au and Au. Our approach simplifies the metallurgies used in classic chip-to-package assemblies by avoiding the use of solder and the concomitant issues of intermetallic formation such as electrical resistance and brittleness. In this paper, we address TCB parameter optimization and material characteristics of these metal-metal TCB joints. The roles of three physical mechanisms on Cu-Cu interface voiding i.e. surface roughness prior to TCB, oxide presence at bonding interface and thermomechanical stress induced by temperature and applied pressure are evaluated in detail. We use specially designed test structures and dies to evaluate the process space. We describe the processing steps for preparing the dielets for assembly on the interconnect fabric (IF). The interconnects are realized using copper contacts on both sides, which are fabricated using copper damascene process and subsequently bonded using Cu-Cu TCB process. For Cu-Cu TCB joints, the diffusion coefficients and activation energies of Cu strongly depend on the surface crystallographic orientation and also on the bonding environment in which the bonding is performed . In our experiments, we employed DC-electro-deposition for making copper contacts. A die-to-substrate bonder was used during the optimization of various process parameters such as pressure, temperature, time and bonding environment. The X-Ray Diffractometer revealed polycrystalline Cu-phases on the contact surface, which were successfully bonded under optimized process conditions [300 ⁰C, 30 min, 10 MPa, ambient pressure ~10--2 mbar]. There are other factors that can affect the copper bonding process such as oxidation. Two kinds of oxides, namely cuprous Oxide (Cu2O) and Cupric Oxide (CuO), are usually formed on the copper surface. This interfacial oxides inhibits the Cu inter-diffusion and grain growth needed to initiate the bond. We have used wet etching techniques such as hydrochloric acid dipping and acetic acid dipping to minimize the oxides . In a classic solder-based reflow process, the solder usually accommodates any topographic irregularities. In the absence of solder, surface planarization to the atomic level is an important requirement that we will address. We have used Chemical Mechanical Planarization (CMP) for surface flatness and have made a comparative study for the as dc-electrodeposited and planarized copper surfaces. The TCB joints are further analyzed qualitatively by making metallographic cross sections. The SEM/FIB analysis shows the presence of small (0.25 µm) to large grain (3 µm) sizes in the interface region. The impact of grain size on mechanical properties of joint is investigated. In addition, smalls void were also found along with the grain boundaries. Our results show that solderless direct Cu-Cu TCB is a viable choice for making fine pitch high-conductivity interconnects.|
|Adeel Ahmad Bajwa, Postdoctoral Fellow
Center for Heterogeneous Integration and Performance Scaling (CHIPS), University of California at Los Angeles
Los Angeles, California