Here is the abstract you requested from the IMAPS_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Evaluating the Effect of SMT Material & Process Variables on Voiding Under QFNs|
|Keywords: Modern solder materials, process control, QFN void mitigation|
|Voiding under bottom terminated components (BTCs) such as Quad-Flat No-lead (QFN) components is a problem which many circuit board assembly houses face on a daily basis. Such components have become very popular in circuit board assembly due to many of their benefits; including their small form factor, excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. Outgassing of flux in the solder paste used to attach QFNs to the PCB during reflow causes voiding under the components, as the gasses cannot escape due to there being virtually no standoff under the QFNs. Voiding can have several serious effects on the performance of QFNs; including reduced mechanical strength of the solder joint and hot spots under the QFN thermal pad since the voids do not conduct heat well. There are many process methods which are utilized in an attempt to mitigate the voiding issue, such as windowpane stencil designs and reflow profile. In this study, we will evaluate the effect of several other variables on voiding under QFNs; including solder paste powder mesh size, PCB surface metallization, and the reflow environment.|
|Maria Durham, Technical Support Engineer