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Fan-Out Wafer Level Packaging: Market and Technology Trends
Keywords: Fan-Out, FO-WLP, Market Trends
The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore’s law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. In order to answer market demands, the industry seeks further performance and functionality boosts in integration. While scaling options remain uncertain in the shorter term and continue to be investigated, the spotlight turns to advanced packages. Emerging packages such as fan-out wafer level packages and 2.5D/3D IC solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve while at the same time adding more functionality through integration. Embedded packages are nowadays not anymore just an interesting approach for specific applications. Benefiting from 3D TSV high cost, these packages could fit the high expectations of the industry. Indeed, added value of embedded packages in terms of integration, reliability and even cost at system level is already clear for manufacturers. Embedded packages lacked success until 2013-2014 because of long time of qualification, few players involved and customer convincing time. The situation changed with new product announcements and strong involvement of some key players, lately most notably TSMC. In this work we will focus on one main type of embedded package of most interest at the moment: Fan-Out wafer level package. The principle of Fan-Out technology is to embed products in a mold compound and allow redistribution layer pitch to be independent from die size. This approach is already mature enough to have high volume products claimed by Nanium and Stats ChipPAC using eWLB type of Fan-Out, with many other developments from OSATs and an aggressive technology from TSMC (inFO). The market for Fan-Out packages in 2014 almost reached $200M, with potential breakthrough events in store in 2016 that could triple the 2015 market and continue further with 32% growth. Understanding the potential of that market and the high demand from telecom industry for a thin and cheap package, other important OSATs like SPIL or J-Devices are willing to enter the market with their own technologies. TSMC is also proposing its inFO process to its customers, confirming that foundries could look at the OSATs reserved market through wafer-level packages. Each player has its own view on how to gain market share and meet the challenges such as cost reduction, panel manufacturing, yield improvement, die shift… The presentation will provide an overview of the products announcements, commercialization roadmaps as well as market forecasts per application. Insights and trends into the different fan-out and embedded die packaging approaches by applications, business models and major players will be reviewed.
J. Azemar,
Villeurbanne , Lyon

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