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3D SiP assembly and reliability for glass substrate with through vias
Keywords: Glass substrate, Through-via, System-in-Package
Applications of Glass substrate for high performance system-in-package (SiP) products have gradually become a promising technology in recent years. Research and development activities are reported in many journal papers and conferences [1, 2]. Consortiums and Alliances are also formed to gather worldwide efforts for developing glass technology. In the past, we have published our development efforts on the process of producing glass substrate with through via and build-up redistribution circuit layers (RDLs) [3]. N. Koizumi [4] first reported glass reliability issues in 2013; and the phenomena he called SE-WA-RE has caused a great concern of using glass as a substrate. Model simulations have indicated that the glass crack is related to the stress buildup by the materials and structure. In this study, we selected a dielectric material/structure set that is designed to be less stressful to the glass substrate. A better reliability result can be expected. In this paper, we will discuss an assembly structure of SiP module using the glass substrate with through-glass via (TGV) where the diameter of TGV is 100μm with thickness at 200μm. The copper plating technique to form the through via conductor is called direct-metal-on-glass (DMoG) which deposits copper directly on glass both in the wall of through vias and on glass surfaces. The first RDL is formed on both surfaces of glass substrate by semi-additive plating (SAP); then followed by build-up RDLs on top of the DMoG RDLs on both sides of the substrate also by SAP with interconnect vias to form connections between DMoG RDLs and build-up RDLs. Finally, solder mask is applied on both sides of the glass substrate leaving pad openings (SRO) for surface finishing, die mounting and printed-circuit board connection purposes. At die mounting side, the SRO is 60μm in diameter with minimum pitch at 150μm. The TGV conductors connect the DMoG RDLs on both sides of the substrate. A mechanical test die with 20μm bump diameter is mounted on the build-up RDL at the substrate top side with daisy-chain design both in the test die and TGV substrate RDLs. Thus, the daisy-chain connection can go from the build-up RDL of the substrate back side to the test die on the top side of the substrate. 500 thermal-cycling test (TCT) has been performed and the daisy-chain resistances are measured before and after the 500 TCT. The shift of daisy-chain resistance has been observed within ±20%.
Ra-Min Tain, Deputy Director
Unimicron Technology Corp.
Hsin-Feng, Hsinchu county, Taiwan
Taiwan ROC


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