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Development and challenges of warpage for fan-out wafer-level package technology
Keywords: fan-out, warpage, wafer-level package
Fan-out wafer-level-packaging (FO-WLP) technology has been widely investigated recently with its advantages of thin form factor structure, cost effective and high performance for wide range application. Reducing wafer warpage is one of the most challenging needs to be addressed for successfully subsequent processes. Therefore, the majorities of studies are focusing on the ratio of die and compound thickness, structure design. In order to optimize the warpage for successfully subsequent processes, it is indispensable to consider whole wafer process including thermal loading and stress. In this study, reduce wafer warpage at each process was proposed in terms of material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. The mutual relationship and effects of material property, compound thickness, and corresponding thermal influences were both investigated and addressed. Key parameters were identified based on FEA modeling results: thickness ratio of die/compound, molding compound materials. Therefore, the geometry design with balanced die/compound ratio is optimal for warpage improvement. The effect of process will be discussed and should be consider for future package warpage characterization. Such findings have been successfully used in process optimization to reduce wafer warapge after grinding process.
Mu-Hsuan Chan,
Siliconware Precision Industries Co., Ltd.
Daya, Taichung , Daya, Taichung
Taiwan


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