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New laser-based FOWLP processes for high I/O applications with ultra-fine line routing and sub 4 um vias.
Keywords: FOWLP, Laser ablation, low temperature polymers
Fan-out Wafer Level Packaging (FOWLP) is a continuing growing packaging trend in microelectronics. Main application is today the single chip packaging with low routing density. The technology has a high potential for high I/O packaging for multi-chip packaging especially for high frequency applications. There are two mayor challenges to realization a high routing density RDL on molded substrates. One is the large pad tolerances to contact the chips. In a classical eWLB like process the chips are placed on a tape and embedded with mold material. The combination of high temperature and pressure during the mold process could lead to an increased die shift. The second point is the resolution limitation of the photo-sensitive dielectric polymers to realize via openings below 10 um. In this paper a new patent pending technology is presented which minimize the die shift below 2 um by a fixation of the chip during the molding process on a carrier. The molding compound with the embedded chips will be released by a laser process from the carrier. A wave length of 248 nm is used which is transparent for a glass carrier and will be absorbed in the first few nm of an adhesive layer. The mold wafer could be released without any force at ambient temperature. The excimer laser is also used for the ablation of the polymer layers to generate a fine line routing. A laser scanning technology together with a quartz mask allows a high throughput in combination of ultra-fine via openings below 4 um. The depth of ablation onto the polymer could be controlled by number of laser pulses and fluence. After via generation into the polymer layer the RDL lines are ablated into the polymer with the half depth of the polymer layer thickness. A landing pad is not necessary in the lines to via design because of the sub-mico meter accuracy of the two laser ablation processes. This allows to realize a fine routing layer density. The vias and lines are metallized by a galvanic process. Standard PIs and PBOs cannot be used because temperatures above 250 C would damage the molding material. Test structures have been design and fabricated by using low cure temperature PI, BCB and ABF as dielectric material to demonstrate the dense routing capability in combination of reconfigured substrates.
Markus Woehrmann, Wafer Level System Integration
Fraunhofer IZM
Berlin, Berlin
Germany


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