Here is the abstract you requested from the IMAPS_2016 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Novel Mold-free Fan-out (MFFO) Wafer Level Package using Silicon Wafer|
|Keywords: Fan-out, Wafer Level Packaging, MFFO|
|Fan-in Wafer Level Packages (WLP) are widely used in smartphones and wearable electronics due to several advantages that include low-cost, fast cycle time, and WLPs are also true chip scale packages with the smallest form-factor. Several engineering advances have significantly increased the pin count of WLP in the last decade. Conventional Fan-in WLP, however, loses on practicality and economy for high pin count devices with high level of integration since silicon die size has to increase to accommodate higher pin count. This need for high levels of integration and high pin count has created the need for Fan-out Wafer Level packaging. Fan-out Wafer level packaging has gained tremendous interest throughout the semiconductor industry, due to advantages in cost and practicality. Traditionally, Fan-out WLPs have been based on encapsulation of silicon dies in a molded reconstituted wafer . These packages are not synergistic with conventional Fan-in WLP processing due to difference in material used for the wafer. In this paper, we present a novel Mold-free Fan-out (MFFO) Wafer Level Package using a Silicon wafer. The core of this technology involves placing Silicon dies in Cavities in a silicon wafer and this process will be presented in this paper. The cavities can be formed in a variety of ways but a practical and low cost way of forming them would be using KOH based wet etch process, and is used in this technology. This Silicon wafer Fan-out package has advantages that are multifold. Using silicon enables full synergy with conventional silicon based Fan-in WLP and hence all existing Fan-in materials, infrastructure, and processing can be leveraged and directly applied to this technology. The thermo-mechanical characteristics of this package are very similar to conventional WLP and therefore all reliability advances and learnings are applicable to this technology. Another benefit is fast cycle time that conventional WLP is capable of. The technology meets all the reliability needs of conventional WLP and the reliability data obtained during the qualification of this technology will be presented in this paper. To the best of our knowledge, this paper is the first to present the concept of Mold-free Silicon wafer based fan-out technology.|
|Vivek Sridharan, Member of Technical Staff
Farmers Branch, Texas